Non-volatile data storage devices, such as universal serial bus (USB) flash memory devices or removable storage cards, have allowed for increased portability of data and software applications. Flash memory devices can enhance data storage density by storing multiple bits in each flash memory cell. For example, Multi-Level Cell (MLC) flash memory devices provide increased storage density by storing 3 bits per cell, 4 bits per cell, or more. Although increasing the number of bits per cell and reducing device feature dimensions may increase storage density of a memory device, a bit error rate of data stored at the memory device may also increase.
Error correction coding (ECC) is often used to correct errors that occur in data read from a memory device. Prior to storage, data may be encoded by an ECC encoder to generate redundant information (e.g. “parity bits”) that may be stored with the data as an ECC codeword. As more parity bits are used, an error correction capacity of the ECC increases and a number of bits required to store the encoded data also increases.
Increasing a number of parity bits improves a correction capability of an ECC scheme. However, decoding latency and power consumption may also increase as the number of parity bits are increased. For a memory device that has relatively few errors when the memory device is new but experiences increased bit errors as the device ages. Using a large number of parity bits increases latency and power consumption over the life of the device even though the additional error correction capability provided by the additional parity bits is not utilized until the device approaches an end of its useful life.